The approach used in building integrated circuits on monolithic pieces of silicon involves the fabrication of successive layers of insulating, conducting, and semiconducting materials. Each layer is patterned to form a structure that performs a specific function, usually linked with surrounding areas and subsequent layers. One of the last layers put on the wafer is a final metal layer which will extend to bonding pads which will ultimately connect the chip circuitry to external devices, such as input and output devices. This metal layer is typically patterned to form an array of substantially parallel conductive runners which are predominately spaced a defined distance apart relative to adjacent runners throughout the array. Additionally, the patterned metal runners have a predominant elevation throughout the array.
Following the patterning of this final metal layer, a passivation layer is deposited over the entire top surface of the wafer. The passivation layer is an insulating and protective layer which prevents mechanical and chemical damage during assembly and packaging. The passivation layer will be finally masked and etched to define patterns corresponding to the bonding regions in which electrical contact to the finished circuit will be made.
The passivation layer preferably provides several attributes. For example, the passivation layer should be impermeable to moisture and sodium atoms, and other highly mobile impurities. It should adhere well to the conductive metal runners as well as to the dielectric layer circuits, with thicker passivation layers generally providing greater protection. It should exhibit low stress and have thermal expansion/contraction properties somewhat aligned with the underlying metal and upper inter-level dielectric. Passivation layers typically comprise one or more of doped SiO.sub.2, spin-on glass (SOG), silicon nitride, oxynitride, and combinations thereof. Passivation technology is described generally in S. Wolf, "Silicon Processing for the VLSI Era", vol. 2-Process Integration, Lattice Press, Sun Beach, Calif., pp. 273-76, 1990, which is hereby incorporated by reference.
A predominant problem with prior art passivation techniques is described with reference to FIG. 1. There illustrated is a semiconductor wafer fragment 10 having a series of metal runners 12, 14 and 16 patterned across a substrate dielectric layer 18. A passivation layer 20 has been deposited atop the wafer over runners 12, 14 and 16 to a very high degree of thickness, as desired. After application of layer 20, a nitride layer such as layer 24, is typically applied. Finally, an overlying layer (not shown) of an organic/plastic-like material such as polyimide is applied atop the wafer to further encapsulate the wafer and result in an upper planer surface.
However, a phenomenon commonly referred to as the "bread-loafing effect" produces a series of voids 22 between adjacent runners within layer 20. No matter how great the thickness of passivation layer 20, voids or passageways 22 tend to be created. Such can provide stress cracks within the wafer and cause out gassing problems during subsequent wafer processing.
It would be highly desirable to provide techniques for providing thick passivating layers atop a wafer and avoid formation of voids or passageways 22.